1. Field of the Invention
This invention relates to a TTL to ECL translator and, more particularly, relates to a TTL to ECL translator which has a fixed threshold voltage over a wide temperature range or whose threshold voltage is tailored to have a specified temperature coefficient.
2. Discussion of Background and Prior Art
Circuit designers are able to choose from a variety of logic families as they design integrated circuits. Their selection will be based on such criteria as power consumption, speed, processes available in-house and compatibility with related circuits. In many cases, in order to achieve compatibility with related circuits and yet utilize the logic family with the desired properties, a circuit designer will design the working circuit in one logic family, e.g. ECL, since it has the lowest propagation delay, and yet provide translators so that the integrated circuit accepts inputs and provides outputs at the voltage levels associated with another logic family, e.g. TTL. If the translators are fabricated on the chip, the integrated circuit would be designated a pseudo-ECL part. Otherwise, external translators can be used; such stand-alone translators include, e.g., the Motorola MC10124 Quad TTL to MECL Translator, the Motorola MC10125 Quad MECL to TTL Translator or the Motorola MC10177 Triple MECL to NMOS Translator. Translation or the shifting of voltage levels is required because each logic family has its own specification for the voltage levels which uniquely define the digital information. For example, with ECL a logic "1" is specified by any voltage more positive than about -0.9 volts while a logic "0" is indicated by any voltage more negative than -1.8 volts; for transistor-transistor logic (TTL) a digital "0" is indicated by any voltage less than 0.8 volts while a digital "1" is indicated for a voltage more positive than 2.0 volts. Similar conventions exist for other logic families such as I.sup.2 L, MOS, RTL and DTL. The most widely utilized families, however, are TTL and ECL. To use integrated circuits of different logic families together it is thus necessary to shift voltage levels to preserve the digital information. While translation can either be carried out externally or on-chip, as described above, it is highly preferred to carry out such translation on board the integrated circuit chip. The use of external translators introduces additional delay and involves separate packages which have to be organized and housed on a printed circuit board.
Various designs for level shifting or translation have been advanced. See, e.g., T. S. Wong, "Write and Read Control Circuit for Semiconductor Memories", U.S. Pat. No. 4,272,811; D. L. Fett et al, "Logic Level Translator", U.S. Pat. No. 3,959,666; D. L. Fett et al, "Logic Level Translator", U.S. Pat. No. 3,974,402; and R. C. Lutz, "High Speed Logic Level Converter", U.S. Pat. No. 3,986,045. These prior art schemes typically are not temperature compensated over either the commercial temperature range (0.degree.-70.degree. C.) or the military temperature range (-55.degree.-125.degree. C.). The result is that the actual input translator threshold will vary from 0.9 volts to 1.9 volts which sometimes makes it difficult to meet the standard input specifications of a maximum low input of V.sub.IL =0.8 v or of a minimum high input of V.sub.IH =2.0 v. A typical prior art TTL to ECL translator is shown in FIG. 1. Transistors 12 and 13 comprise an ECL type differential buffer which have a threshold voltage impressed on the base of transistor 13 and an input voltage impressed on the base of transistor 12. Current from V.sub.CC supply line 23 to ground line 24 will toggle between transistors 12 and 13 depending on whichever base voltage is higher, the threshold voltage, V.sub.T, or the input voltage, V.sub.IN. The threshold voltage, V.sub.T, is supplied at node b. In operation, as described in detail subsequently, the voltage drop across diode 14 will vary with temperature and therefore the voltage supplied at node b will vary so that the sense of the ECL output levels on terminals c and d for a given input voltage V.sub.IN are not necessarily the same over a wide range in temperature. As a consequence of these variations, noise margins are reduced. Also, it is not readily possible to test parts with definition because the threshold is too close to the specified limit values to be able to measure and guarantee. And, in order to fabricate a functional translator using the design of the prior art, the circuit had to be placed in a good location on the chip and given an adequate ground line.
It is therefore an object of the present invention to provide a TTL to ECL translator which is temperature compensated.
It is another object of the present invention to provide a translator for shifting logic signals from the levels of one family to the levels of another family which possesses wide noise margins.
It is an additional object of the present invention to provide a TTL to ECL translator which may readily be tested.